Linux sagir-us1.hostever.us 5.14.0-570.51.1.el9_6.x86_64 #1 SMP PREEMPT_DYNAMIC Wed Oct 8 09:41:34 EDT 2025 x86_64
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User : georgeto
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android
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
byteorder
[ DIR ]
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2026-05-20 11:46
caif
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drwxr-xr-x
2026-05-20 11:46
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2026-05-20 11:46
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2026-05-20 11:46
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2026-05-20 11:46
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2026-05-20 11:46
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drwxr-xr-x
2026-05-20 11:46
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drwxr-xr-x
2026-05-20 11:46
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[ DIR ]
drwxr-xr-x
2026-05-20 11:46
netfilter_ipv4
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
netfilter_ipv6
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
nfsd
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
raid
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
sched
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
spi
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
sunrpc
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
surface_aggregator
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
tc_act
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
tc_ematch
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
usb
[ DIR ]
drwxr-xr-x
2026-05-20 11:46
a.out.h
6.73
KB
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2026-05-19 19:43
acct.h
3.82
KB
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2026-05-19 19:43
acrn.h
16.29
KB
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2026-05-19 19:43
adb.h
1.11
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adfs_fs.h
993
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2026-05-19 19:43
affs_hardblocks.h
1.54
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2026-05-19 19:43
agpgart.h
3.85
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2026-05-19 19:43
aio_abi.h
3.32
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2026-05-19 19:43
am437x-vpfe.h
3.59
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2026-05-19 19:43
apm_bios.h
3.6
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2026-05-19 19:43
arcfb.h
213
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arm_sdei.h
2.69
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2026-05-19 19:43
aspeed-lpc-ctrl.h
1.74
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aspeed-p2a-ctrl.h
1.86
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atalk.h
1023
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atm.h
7.7
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atm_eni.h
648
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atm_he.h
406
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atm_idt77105.h
955
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atm_nicstar.h
1.25
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atm_tcp.h
1.58
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atm_zatm.h
1.5
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atmapi.h
952
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atmarp.h
1.27
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atmbr2684.h
3.19
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atmclip.h
576
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atmdev.h
7.5
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atmioc.h
1.61
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atmlec.h
2.33
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atmmpc.h
4.13
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atmppp.h
639
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atmsap.h
4.85
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atmsvc.h
1.81
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audit.h
21.06
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auto_dev-ioctl.h
4.87
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auto_fs.h
6.28
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auto_fs4.h
451
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auxvec.h
1.56
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ax25.h
2.76
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batadv_packet.h
19.87
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batman_adv.h
16.49
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baycom.h
883
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bcm933xx_hcs.h
419
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bfs_fs.h
1.86
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binfmts.h
776
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bits.h
447
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blkpg.h
904
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blktrace_api.h
4.59
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blkzoned.h
6.34
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bpf.h
272.11
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bpf_common.h
1.33
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bpf_perf_event.h
529
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bpfilter.h
465
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bpqether.h
981
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bsg.h
2.44
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bt-bmc.h
572
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btf.h
5.46
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btrfs.h
29.85
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btrfs_tree.h
25.22
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cachefiles.h
1.61
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2026-05-19 19:43
can.h
11.23
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capability.h
13.17
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capi.h
3.05
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cciss_defs.h
3.2
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cciss_ioctl.h
2.7
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ccs.h
767
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cdrom.h
28.87
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cec-funcs.h
53.14
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cec.h
40.47
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cfm_bridge.h
1.42
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2026-05-19 19:43
cgroupstats.h
2.17
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2026-05-19 19:43
chio.h
5.16
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close_range.h
377
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cm4000_cs.h
1.76
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cn_proc.h
4.05
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2026-05-19 19:43
coda.h
17.79
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coff.h
12.25
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2026-05-19 19:43
connector.h
2.2
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const.h
987
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coresight-stm.h
747
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cramfs_fs.h
3.47
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cryptouser.h
5.2
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cuda.h
905
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cxl_mem.h
7.73
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cycx_cfm.h
2.92
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dcbnl.h
24.7
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dccp.h
6.29
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devlink.h
22.77
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dlm.h
2.49
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dlm_device.h
2.48
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dlm_netlink.h
1.13
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dlm_plock.h
894
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dlmconstants.h
4.96
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dm-ioctl.h
11.48
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dm-log-userspace.h
14.83
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dma-buf.h
5.12
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dma-heap.h
1.36
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dn.h
4.53
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dns_resolver.h
3.86
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dpll.h
8.56
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dqblk_xfs.h
9.17
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edd.h
5.47
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efs_fs_sb.h
2.17
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elf-em.h
2.57
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elf-fdpic.h
1.1
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elf.h
14.69
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errno.h
23
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errqueue.h
1.94
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erspan.h
1.03
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ethtool.h
101.42
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ethtool_netlink.h
6.17
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ethtool_netlink_generated.h
19.17
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eventfd.h
264
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eventpoll.h
2.84
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f2fs.h
3.22
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fadvise.h
842
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falloc.h
3.56
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fanotify.h
7.7
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2026-05-19 19:43
fb.h
16.09
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fcntl.h
4.22
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fd.h
11.83
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fdreg.h
5.24
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fib_rules.h
1.99
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fiemap.h
2.71
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filter.h
2.16
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2026-05-19 19:43
firewire-cdev.h
43.2
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firewire-constants.h
3.16
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fou.h
819
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fpga-dfl.h
8.52
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fs.h
12.88
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fscrypt.h
6.41
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fsi.h
2.2
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fsl_hypervisor.h
7.13
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fsl_mc.h
734
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fsmap.h
4.29
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fsverity.h
3.11
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fuse.h
25.36
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futex.h
5.98
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gameport.h
897
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gen_stats.h
1.49
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2026-05-19 19:43
genetlink.h
2.19
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2026-05-19 19:43
gfs2_ondisk.h
14.43
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2026-05-19 19:43
gpio.h
19.46
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2026-05-19 19:43
gsmmux.h
4.4
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gtp.h
734
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handshake.h
1.61
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hash_info.h
971
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hdlc.h
637
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hdlcdrv.h
2.84
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hdreg.h
22.17
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2026-05-19 19:43
hid.h
2.04
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hiddev.h
6.2
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hidraw.h
1.95
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2026-05-19 19:43
hpet.h
743
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hsr_netlink.h
1.08
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hw_breakpoint.h
742
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hyperv.h
10.89
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i2c-dev.h
1.83
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2026-05-19 19:43
i2c.h
6.73
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i2o-dev.h
11.28
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i8k.h
1.49
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icmp.h
4.67
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icmpv6.h
4.2
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2026-05-19 19:43
idxd.h
9.11
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2026-05-19 19:43
if.h
10.67
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if_addr.h
1.84
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if_addrlabel.h
721
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if_alg.h
1.53
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if_arcnet.h
3.63
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if_arp.h
6.41
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if_bonding.h
5.02
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if_bridge.h
20.27
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if_cablemodem.h
986
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if_eql.h
1.32
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if_ether.h
8.21
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if_fc.h
1.7
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if_fddi.h
4.27
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if_hippi.h
4.14
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if_infiniband.h
1.22
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if_link.h
52.92
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if_ltalk.h
210
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if_macsec.h
6.35
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if_packet.h
7.99
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if_phonet.h
424
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if_plip.h
660
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if_ppp.h
29
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if_pppol2tp.h
3.23
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if_pppox.h
4.76
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if_slip.h
872
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if_team.h
2.54
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if_tun.h
4
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if_tunnel.h
5.36
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if_vlan.h
1.79
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if_x25.h
881
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if_xdp.h
5.29
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ife.h
351
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igmp.h
2.99
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2026-05-19 19:43
ila.h
1.22
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in.h
10.24
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in6.h
7.36
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2026-05-19 19:43
in_route.h
936
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inet_diag.h
4.9
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inotify.h
3.21
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input-event-codes.h
29.5
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input.h
15.84
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20.4
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ioctl.h
163
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iommufd.h
36.45
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ioprio.h
4.08
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ip.h
4.7
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ip6_tunnel.h
1.91
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ip_vs.h
13.8
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ipc.h
2.05
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ipmi.h
15.08
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ipmi_bmc.h
488
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ipmi_msgdefs.h
3.35
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ipmi_ssif_bmc.h
441
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ipsec.h
947
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ipv6.h
4.07
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ipv6_route.h
1.86
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ipx.h
2.29
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irqnr.h
104
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iso_fs.h
6.33
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14.92
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ivtv.h
2.95
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ivtvfb.h
1.18
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6.66
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joystick.h
3.35
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kcm.h
822
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522
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1.92
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kd.h
6.3
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kdev_t.h
383
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kernel-page-flags.h
900
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kernel.h
194
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kernelcapi.h
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kexec.h
2.05
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keyboard.h
13.14
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keyctl.h
5.86
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kfd_ioctl.h
57.06
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kfd_sysfs.h
5.25
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kvm.h
47.24
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kvm_para.h
1001
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l2tp.h
5.61
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landlock.h
11.55
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libc-compat.h
8.09
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limits.h
937
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lirc.h
7.95
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llc.h
3.09
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loadpin.h
834
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loop.h
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lp.h
4.09
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lsm.h
1.51
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lwtunnel.h
2.31
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magic.h
3.73
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major.h
4.55
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map_to_7segment.h
6.45
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matroxfb.h
1.43
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max2175.h
1.01
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mdio.h
23.78
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media-bus-format.h
6.75
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media.h
12.46
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mei.h
3.4
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mei_uuid.h
738
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membarrier.h
9.14
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memfd.h
1.43
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mempolicy.h
2.51
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2.47
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mii.h
9.27
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minix_fs.h
2.07
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mman.h
1.75
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mmtimer.h
2.07
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module.h
293
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mount.h
4.9
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mpls.h
2.25
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mpls_iptunnel.h
761
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mptcp.h
3.67
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mptcp_pm.h
4.3
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mqueue.h
2.15
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mroute.h
5.78
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mroute6.h
4.81
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mrp_bridge.h
1.67
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msdos_fs.h
6.57
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msg.h
3.31
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mshv.h
7.93
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mtio.h
7.98
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nbd-netlink.h
2.35
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nbd.h
3.77
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ncsi.h
4.71
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ndctl.h
6.67
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neighbour.h
5.91
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net.h
2.04
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net_dropmon.h
2.85
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net_namespace.h
715
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net_shaper.h
2.52
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net_tstamp.h
6.3
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netconf.h
614
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netdev.h
5.65
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netdevice.h
2.2
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netfilter.h
1.69
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netfilter_arp.h
445
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netfilter_bridge.h
1.14
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netfilter_decnet.h
1.72
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netfilter_ipv4.h
1.45
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netfilter_ipv6.h
1.35
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netlink.h
12.09
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netlink_diag.h
1.49
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netrom.h
807
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nexthop.h
3.97
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nfc.h
10.95
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nfs.h
4.36
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nfs2.h
1.43
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nfs3.h
2.4
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nfs4.h
6.54
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nfs4_mount.h
1.89
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nfs_fs.h
1.62
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nfs_idmap.h
2.19
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nfs_mount.h
2.09
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nfsacl.h
718
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nfsd_netlink.h
1.95
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nilfs2_api.h
7.41
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nilfs2_ondisk.h
17.66
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nitro_enclaves.h
12.85
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nl80211.h
341.33
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nsfs.h
639
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nubus.h
8
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nvme_ioctl.h
2.43
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nvram.h
532
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omap3isp.h
20.36
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omapfb.h
5.78
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oom.h
511
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openat2.h
1.42
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openvswitch.h
40.75
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packet_diag.h
1.63
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param.h
141
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parport.h
3.56
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patchkey.h
892
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pci.h
1.35
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pci_regs.h
61.89
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pcitest.h
920
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perf_event.h
42.68
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personality.h
2.05
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pfkeyv2.h
10.32
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pfrut.h
7.8
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pg.h
2.34
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phantom.h
1.62
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phonet.h
4.57
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pidfd.h
256
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pkt_cls.h
18.65
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pkt_sched.h
28.75
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pktcdvd.h
2.63
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pmu.h
5.32
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poll.h
22
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posix_acl.h
1.22
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posix_acl_xattr.h
1.09
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posix_types.h
1.07
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ppdev.h
3.21
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ppp-comp.h
2.47
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ppp-ioctl.h
5.59
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ppp_defs.h
5.43
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pps.h
4.62
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pr.h
1.59
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prctl.h
10.81
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psample.h
2.57
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psci.h
5.21
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psp-dbc.h
5.16
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psp-sev.h
7.59
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ptp_clock.h
7.35
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ptrace.h
4.29
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qemu_fw_cfg.h
2.41
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qnx4_fs.h
2.27
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qnxtypes.h
624
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qrtr.h
893
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quota.h
6.16
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radeonfb.h
360
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random.h
1.38
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rds.h
10.91
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reboot.h
1.31
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reiserfs_fs.h
775
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reiserfs_xattr.h
533
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remoteproc_cdev.h
1.08
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resource.h
2.32
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rfkill.h
6.45
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rio_cm_cdev.h
3.17
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rio_mport_cdev.h
9.11
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rkisp1-config.h
30.63
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romfs_fs.h
1.21
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rose.h
2.18
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route.h
2.28
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rpl.h
814
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rpl_iptunnel.h
424
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rpmsg.h
1.03
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rpmsg_types.h
288
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rseq.h
4.79
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rtc.h
5.19
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rtnetlink.h
20.8
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rxrpc.h
4.81
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scc.h
4.52
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sched.h
6.12
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scif_ioctl.h
6.23
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screen_info.h
2.42
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sctp.h
35.18
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seccomp.h
5.6
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securebits.h
2.64
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sed-opal.h
5.29
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seg6.h
1.14
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seg6_genl.h
589
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seg6_hmac.h
423
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seg6_iptunnel.h
984
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seg6_local.h
3.78
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selinux_netlink.h
1.17
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sem.h
2.98
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serial.h
4.9
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serial_core.h
4.93
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serial_reg.h
15.65
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serio.h
2.09
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sev-guest.h
2.47
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shm.h
3.71
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signal.h
388
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signalfd.h
1.2
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smc.h
8.46
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smc_diag.h
2.88
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smiapp.h
1.03
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snmp.h
14.01
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sock_diag.h
1.27
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socket.h
919
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sockios.h
6.69
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sonet.h
2.24
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sonypi.h
5.18
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sound.h
1.21
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soundcard.h
44.96
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stat.h
7.23
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stddef.h
1.69
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stm.h
1.25
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string.h
238
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suspend_ioctls.h
1.4
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swab.h
6.76
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switchtec_ioctl.h
5.14
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sync_file.h
3.49
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synclink.h
8.77
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sysctl.h
25.3
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Save
Rename
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * V4L2 DV timings header. * * Copyright (C) 2012-2016 Hans Verkuil <hans.verkuil@cisco.com> */ #ifndef _V4L2_DV_TIMINGS_H #define _V4L2_DV_TIMINGS_H #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6)) /* Sadly gcc versions older than 4.6 have a bug in how they initialize anonymous unions where they require additional curly brackets. This violates the C1x standard. This workaround adds the curly brackets if needed. */ #define V4L2_INIT_BT_TIMINGS(_width, args...) \ { .bt = { _width , ## args } } #else #define V4L2_INIT_BT_TIMINGS(_width, args...) \ .bt = { _width , ## args } #endif /* CEA-861-F timings (i.e. standard HDTV timings) */ #define V4L2_DV_BT_CEA_640X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X480I59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \ 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ { 4, 3 }, 6) \ } #define V4L2_DV_BT_CEA_720X480P59_94 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \ 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \ } /* Note: these are the nominal timings, for HDMI links this format is typically * double-clocked to meet the minimum pixelclock requirements. */ #define V4L2_DV_BT_CEA_720X576I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \ 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \ { 4, 3 }, 21) \ } #define V4L2_DV_BT_CEA_720X576P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \ 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \ V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \ } #define V4L2_DV_BT_CEA_1280X720P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \ } #define V4L2_DV_BT_CEA_1280X720P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \ } #define V4L2_DV_BT_CEA_1280X720P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \ } #define V4L2_DV_BT_CEA_1280X720P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \ } #define V4L2_DV_BT_CEA_1280X720P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 720, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \ } #define V4L2_DV_BT_CEA_1920X1080P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \ } #define V4L2_DV_BT_CEA_1920X1080P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \ } #define V4L2_DV_BT_CEA_1920X1080P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \ } #define V4L2_DV_BT_CEA_1920X1080I50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \ } #define V4L2_DV_BT_CEA_1920X1080P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \ } #define V4L2_DV_BT_CEA_1920X1080I60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | \ V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \ } #define V4L2_DV_BT_CEA_1920X1080P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \ } #define V4L2_DV_BT_CEA_3840X2160P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ { 0, 0 }, 93, 3) \ } #define V4L2_DV_BT_CEA_3840X2160P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \ V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \ } #define V4L2_DV_BT_CEA_3840X2160P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ { 0, 0 }, 95, 1) \ } #define V4L2_DV_BT_CEA_3840X2160P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \ } #define V4L2_DV_BT_CEA_3840X2160P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \ } #define V4L2_DV_BT_CEA_4096X2160P24 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \ { 0, 0 }, 98, 4) \ } #define V4L2_DV_BT_CEA_4096X2160P25 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \ } #define V4L2_DV_BT_CEA_4096X2160P30 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \ } #define V4L2_DV_BT_CEA_4096X2160P50 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \ } #define V4L2_DV_BT_CEA_4096X2160P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \ V4L2_DV_BT_STD_CEA861, \ V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \ V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \ } /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */ #define V4L2_DV_BT_DMT_640X350P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \ 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_720X400P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \ 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* VGA resolutions */ #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94 #define V4L2_DV_BT_DMT_640X480P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_640X480P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \ 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } /* SVGA resolutions */ #define V4L2_DV_BT_DMT_800X600P56 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P72 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_800X600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \ 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_848X480P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(848, 480, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768I43 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 1, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \ V4L2_DV_BT_STD_DMT, 0) \ } /* XGA resolutions */ #define V4L2_DV_BT_DMT_1024X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \ 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1024X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* XGA+ resolution */ #define V4L2_DV_BT_DMT_1152X864P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1152, 864, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60 /* WXGA resolutions */ #define V4L2_DV_BT_DMT_1280X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \ 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X800P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \ 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1280X800P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \ 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1280X960P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X960P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \ 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA resolutions */ #define V4L2_DV_BT_DMT_1280X1024P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1280X1024P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \ 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1360X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1360X768P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \ 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1366X768P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1366X768P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1366, 768, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* SXGA+ resolutions */ #define V4L2_DV_BT_DMT_1400X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1400X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1400X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WXGA+ resolutions */ #define V4L2_DV_BT_DMT_1440X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1440X900P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \ 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1440X900P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \ 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1600X900P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 900, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* UXGA resolutions */ #define V4L2_DV_BT_DMT_1600X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P65 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P70 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1600X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* WSXGA+ resolutions */ #define V4L2_DV_BT_DMT_1680X1050P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1680X1050P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \ 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1680X1050P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \ 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1792X1344P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \ 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1792X1344P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \ 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1856X1392P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \ 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1856X1392P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \ 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60 /* WUXGA resolutions */ #define V4L2_DV_BT_DMT_1920X1200P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1200P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \ 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_1920X1200P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \ 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_1920X1440P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \ 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, 0) \ } #define V4L2_DV_BT_DMT_1920X1440P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \ 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2048X1152P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \ 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \ V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \ } /* WQXGA resolutions */ #define V4L2_DV_BT_DMT_2560X1600P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_2560X1600P60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P75 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P85 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \ 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \ } #define V4L2_DV_BT_DMT_2560X1600P120_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \ 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* 4K resolutions */ #define V4L2_DV_BT_DMT_4096X2160P60_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \ 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \ V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \ V4L2_DV_FL_REDUCED_BLANKING) \ } /* SDI timings definitions */ /* SMPTE-125M */ #define V4L2_DV_BT_SDI_720X487I60 { \ .type = V4L2_DV_BT_656_1120, \ V4L2_INIT_BT_TIMINGS(720, 487, 1, \ V4L2_DV_HSYNC_POS_POL, \ 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \ V4L2_DV_BT_STD_SDI, \ V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \ } #endif